The present invention relates to methods for fabricating metal wiring layers of a semiconductor device, and more specifically, to methods of fabricating interconnect structures for semiconductor devices with minimized resistance and improved time dependent dielectric breakdown (TDDB) performance.
An integrated circuit (IC) device may be formed with millions of transistors and other circuit elements that are fabricated on a single silicon crystal substrate (wafer). For the IC device to be functional, multi-level or multi-layered interconnection schemes such as, for example, dual damascene wiring (interconnect structures) or wiring formed by subtractive etch, are fabricated using BEOL (back end of line) techniques to connect the circuit elements distributed on the surface of the device. BEOL technologies must be continuously optimized through changes in process flows and material used in order to build high performance structures as critical dimensions decrease. For example, etching of small profiles using thin masking layers becomes increasingly problematic with regard to etch profile control (controlling shape of hole or trench being formed) or control of etching damage and residues. Maximizing metal volume for a given space is difficult with current technologies.